Alleviating line end shortening by extending phase shifters

ABSTRACT

One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.

RELATED APPLICATION

[0001] This application hereby claims priority under 35 U.S.C. § 119 toU.S. Provisional Patent Application No. 60/281,385 filed Apr. 3, 2001.

BACKGROUND

[0002] 1. Field of the Invention

[0003] The invention relates to the process of fabricating semiconductorchips. More specifically, the invention relates to a method and anapparatus that extends phase shifters to alleviate line end shorteningand provide better gate critical dimension control during an opticallithography process for manufacturing an integrated circuit.

[0004] 2. Related Art

[0005] Recent advances in integrated circuit technology have largelybeen accomplished by decreasing the feature size of circuit elements ona semiconductor chip. As the feature size of these circuit elementscontinues to decrease, circuit designers are forced to deal withproblems that arise as a consequence of the optical lithography processthat is typically used to manufacture integrated circuits. This opticallithography process generally begins with the formation of a photoresistlayer on the surface of a semiconductor wafer. A mask composed of opaqueregions, which are generally formed of chrome, and light-transmissiveclear regions (chromeless), which are generally formed of quartz, isthen positioned over this photoresist coated wafer. (Note that the term“mask” as used in this specification is meant to include the term“retical.”) Light is then shone on the mask from a visible light sourceor an ultraviolet light source.

[0006] This light is generally reduced and focused through an opticalsystem that contains a number of lenses, filters and mirrors. The lightpasses through the clear regions of the mask and exposes the underlyingphotoresist layer. At the same time, the light is blocked by opaqueregions of mask, leaving underlying portions of the photoresist layerunexposed.

[0007] The exposed photoresist layer is then developed, typicallythrough chemical removal of the exposed/non-exposed regions of thephotoresist layer. The end result is a semiconductor wafer with aphotoresist layer having a desired pattern. This pattern can then beused for etching underlying regions of the wafer.

[0008] One problem that arises during the optical lithography process is“line end shortening” and “pullback” caused by optical effects. Forexample, the upper portion of FIG. 1 illustrates a design of atransistor with a polysilicon line 102, running from left to right, thatforms a gate region used to electrically couple an upper diffusionregion with a lower diffusion region. The lower portion of FIG. 1illustrates the actual printed image that results from the design.

[0009] Note that because of optical effects and resist pullback there isa significant amount of line end shortening. This line end shortening isdue to optical effects that cause the light to expose more of the resistunder a line end than under other portions of the line.

[0010] Note that polysilicon line 102 has been narrowed using opticalphase shifting in order to improve the performance of the transistor byreducing the resistance through the gate region. Phase shifters areoften incorporated into a mask in order to achieve line widths that aresmaller than the wavelength of the light that is used to expose thephotoresist layer through the mask. During phase shifting, thedestructive interference caused by two adjacent clear areas on a mask isused to create an unexposed area on the photoresist layer. This isaccomplished by exploiting the fact that light passing through a mask'sclear regions exhibits a wave characteristic having a phase that is afunction of the distance the light travels through the mask material. Byplacing two clear areas adjacent to each other on the mask, one ofthickness t₁ and the other of thickness t₂, one can obtain a desiredunexposed area on the underlying photoresist layer caused byinterference. By varying the thickness t₁ and t₂ appropriately, thelight exiting the material of thickness t₂ is 180 degrees out of phasewith the light exiting the material of thickness t₁. Phase shifting isdescribed in more detail in U.S. Pat. No. 5,858,580, entitled “PhaseShifting Circuit Manufacture Method and Apparatus,” by inventorsYao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan.12, 1999, which is hereby incorporated by reference.

[0011] In order to compensate for line end shortening, designers oftenadd optical proximity correction (OPC) features, such as “hammer heads,”onto line ends. For example, in FIG. 2A, a hammerhead 215 is added ontoan endcap 216 of a transistor in order to reduce the problem of line endshortening in some situations. However, note that hammerhead 215 maygive rise the design rule violations that can potentially cause bridgingbetween the hammerhead and polysilicon line 202.

[0012] This bridging problem can be alleviated by introducing aseparation between hammerhead 215 and polysilicon line 202. However,introducing such a separation increases the size of the circuit element,which means that fewer circuit elements can be integrated into asemiconductor chip.

[0013] What is needed is a method and an apparatus for mitigating theline end shortening problem in transistor endcaps, while reducing theimpact of OPC features, such as hammerheads.

SUMMARY

[0014] One embodiment of the invention provides a system and a methodfor reducing line end shortening and improved gate critical dimensioncontrol during an optical lithography process for manufacturing anintegrated circuit. The system operates by receiving a specification ofthe integrated circuit, wherein the specification defines transistorsthat include gates. Next, the system identifies a gate within thespecification, wherein the gate includes an endcap that is susceptibleto line end shortening during the optical lithography process. Thesystem then extends a phase shifter used to form the gate, so that thephase shifter defines at least a portion of the endcap and therebyreduces line end shortening of the endcap due to optical effects.

[0015] In one embodiment of the invention, extending the phase shifterinvolves extending the phase shifter past the endcap.

[0016] In one embodiment of the invention, extending the phase shifterinvolves extending the phase shifter so that it covers at least part ofthe endcap, but does not extend past the endcap. In a variation on thisembodiment, the phase shifter extends past the endcap.

[0017] In one embodiment of the invention, the system automaticallychecks design rules that specify a minimum distance between the phaseshifter and other structures within the integrated circuit.

[0018] In one embodiment of the invention, the system additionally marksthe endcap to prevent subsequent optical proximity correction (OPC) ofthe endcap. In a variation on this embodiment, the system subsequentlyapplies OPC to the layout, without applying OPC to endcaps that havebeen marked.

[0019] In one embodiment of the invention, if the endcap has beenmodified through optical proximity correction (OPC), the system replacesthe modified endcap with an (ideal) unmodified endcap.

[0020] In one embodiment of the invention, if the endcap is notstraight, the system replaces the endcap with a straight endcap.

BRIEF DESCRIPTION OF THE FIGURES

[0021]FIG. 1 illustrates the line end shortening problem.

[0022]FIG. 2A illustrates the use of a hammerhead to compensate for theline end shortening problem.

[0023]FIG. 2B illustrates the use of an extended phase shifter toalleviate the line end shortening problem in accordance with anembodiment of the invention.

[0024]FIG. 3 illustrates the replacement of endcaps that are notstraight or endcaps that have been modified with straight unmodifiedendcaps in accordance with an embodiment of the invention.

[0025]FIG. 4 is a flow chart illustrating the wafer fabrication processin accordance with an embodiment of the invention.

[0026]FIG. 5 is a flow chart illustrating the process of extending aphase shifter to alleviate the line end shortening problem for atransistor endcap in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

[0027] Extended Phase Shifter

[0028]FIG. 2B illustrates the use of an extended phase shifter toalleviate the line end shortening problem in accordance with anembodiment of the invention. The circuit layout in FIG. 2B is the sameas the circuit layout FIG. 2A, except that the phase shifter comprisedof, zero-degree clear region 208, chromium regulator 212 and 180-degreeclear region 210, has been extended so that it covers at least part ofendcap 216 (illustrated in FIG. 2A).

[0029] This alleviates the optical line end shortening problem forendcap 216 because the destructive interference of the phase shifterlessens the incidental exposure problem that causes the line endshortening around endcap 216.

[0030] Note that the phase shifter may extend past endcap 216 if thephase shifter does not interfere with other features in the circuit.Otherwise, the phase shifter may extend to cover at least part of endcap216, but not past endcap 216, so that the phase shifter defines at leasta portion of the boundary of endcap 216.

[0031] Note that by extending the phase shifter in this way, OPCfeatures such as hammerhead 215 are no longer required. Hence, thepotential design rule violations caused by these OPC features can beavoided.

[0032] Endcap Replacement

[0033]FIG. 3 illustrates the replacement of endcaps that are notstraight or endcaps that have been modified with straight unmodifiedendcaps in accordance with an embodiment of the invention. In FIG. 3, anumber of polysilicon lines 304-307 form a set of pass transistors inactive diffusion region 302. Some of these polysilicon lines, such aspolysilicon lines 304 and 307, have endcaps with OPC features that arebecome unnecessary if there exists an extended phase shifter. Otherpolysilicon lines, 305 and 306, are not straight.

[0034] When an extended phase shifter is used to form the endcaps inpolysilicon lines 304-307, the OPC features and non-straight endcapsbecome unnecessary. Consequently, these endcaps are replaced byunmodified straight endcaps as is illustrated by the dotted lines inFIG. 3.

[0035] Wafer Fabrication Process

[0036]FIG. 4 is a flow chart illustrating the wafer fabrication processin accordance with an embodiment of the invention. The system starts byapplying the resist coating to the top surface of a wafer (step 402).Next, the system bakes the resist layer (step 404). The system thenpositions the first mask over the photoresist layer (step 406), and thenexposes the photoresist layer through the first mask (step 408). Next,the system positions the second mask over the photoresist layer (step410), and then exposes the photoresist layer through the second mask(step 412). Note that the first mask and/or the second mask may includephase shifters.

[0037] The system then bakes the wafer again (step 414) beforedeveloping the photoresist layer (step 416). Next, either a chemicaletching or ion implantation step takes place (step 418) before thephotoresist layer is removed (step 420). Finally, a new layer ofmaterial can be added and the process can be repeated for the new layer(step 422).

[0038] Process of Extending a Phase Shifter

[0039]FIG. 5 is a flow chart illustrating the process of extending aphase shifter to alleviate the line end shortening problem for atransistor endcap in accordance with an embodiment of the invention. Theprocess starts when the system receives a specification of the circuitin some format, such as GDSII stream format (step 502). Next, the systemidentifies gates within transistors that have endcaps that the designerdesires to apply phase shifting to, and that are susceptible to line endshortening problems (step 504).

[0040] For these identified gates, the system extends phase shiftersbeyond the active region, for example in FIG. 2B past active diffusionregions 204 and 206 (step 506). Note that this may involve extending thephase shifter beyond the endcap, which in some cases is preferable, oralternatively, extending the phase shifter to cover part or all of theendcap without extending beyond the endcap. Also note that in oneembodiment of the invention, extended phase shifters can be insertedinto areas that were not originally targeted for phase shifting in orderto alleviate the line end shortening problem.

[0041] Next, the system checks design rules to ensure that there existsa pre-specified minimum distance between the extended shifter and otherpolysilicon features in the circuit (step 508). If a design ruleviolation is detected, an error can be generated, and corrective actioncan be taken by either modifying the polysilicon feature or by modifyingthe extended shifter.

[0042] The system also marks the identified endcaps to ensure that theendcaps are not modified during a subsequent OPC process (step 510).

[0043] Additionally, if an identified endcap has been modified toinclude an OPC feature or if the endcap is not straight, the endcap canbe replaced with a unmodified straight endcap as is illustrated in FIG.3 (step 512).

[0044] Finally, an additional OPC process can be applied to unmarkedfeatures within the specification of the circuit (step 514).

[0045] The preceding description is presented to enable any personskilled in the art to make and use the invention, and is provided in thecontext of a particular application and its requirements. Variousmodifications to the disclosed embodiments will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to other embodiments and applications without departing fromthe spirit and scope of the invention. Thus, the invention is notintended to be limited to the embodiments shown, but is to be accordedthe widest scope consistent with the principles and features disclosedherein.

[0046] The data structures and code described in this detaileddescription are typically stored on a computer readable storage medium,which may be any device or medium that can store code and/or data foruse by a computer system. This includes, but is not limited to, magneticand optical storage devices such as disk drives, magnetic tape, CDs(compact discs) and DVDs (digital versatile discs or digital videodiscs), and computer instruction signals embodied in a transmissionmedium (with or without a carrier wave upon which the signals aremodulated). For example, the transmission medium may include acommunications network, such as the Internet.

[0047] The foregoing descriptions of embodiments of the invention havebeen presented for purposes of illustration and description only. Theyare not intended to be exhaustive or to limit the invention to the formsdisclosed. Accordingly, many modifications and variations will beapparent to practitioners skilled in the art. Additionally, the abovedisclosure is not intended to limit the invention. The scope of theinvention is defined by the appended claims.

What is claimed is:
 1. A method for reducing line end shortening duringan optical lithography process for manufacturing an integrated circuit,comprising: receiving a specification of the integrated circuit, whereinthe specification defines transistors that include gates; identifying agate within the specification, wherein the gate includes an endcap thatis susceptible to line end shortening during the optical lithographyprocess; and extending a phase shifter used to form the gate beyond anassociated active region, so that the phase shifter defines at least aportion of the endcap and thereby reduces line end shortening of theendcap due to optical effects.
 2. The method of claim 1, whereinextending the phase shifter involves extending the phase shifter pastthe endcap.
 3. The method of claim 1, wherein extending the phaseshifter involves extending the phase shifter so that it covers at leastpart of the endcap, but does not extend past the endcap.
 4. The methodof claim 1, further comprising automatically checking design rules thatspecify a minimum distance between the phase shifter and otherstructures within the integrated circuit.
 5. The method of claim 1,further comprising marking the endcap to prevent subsequent opticalproximity correction (OPC) of the endcap.
 6. The method of claim 5,further comprising applying optical proximity correction (OPC) to thespecification of the integrated circuit, wherein the OPC is not appliedto endcaps that have been marked.
 7. The method of claim 1, furthercomprising, if the endcap includes modifications for optical proximitycorrection (OPC), removing the modifications.
 8. The method of claim 1,further comprising, if the endcap is not straight, replacing the endcapwith a straight endcap.
 9. A computer-readable storage medium storinginstructions that when executed by a computer cause the computer toperform a method for reducing line end shortening during an opticallithography process for manufacturing an integrated circuit, the methodcomprising: receiving a specification of the integrated circuit, whereinthe specification defines transistors that include gates; identifying agate within the specification, wherein the gate includes an endcap thatis susceptible to line end shortening during the optical lithographyprocess; and extending a phase shifter used to form the gate beyond anassociated active region, so that the phase shifter defines at least aportion of the endcap and thereby reduces line end shortening of theendcap due to optical effects.
 10. The computer-readable storage mediumof claim 9, wherein extending the phase shifter involves extending thephase shifter past the endcap.
 11. The computer-readable storage mediumof claim 9, wherein extending the phase shifter involves extending thephase shifter so that it covers at least part of the endcap, but doesnot extend past the endcap.
 12. The computer-readable storage medium ofclaim 9, wherein the method further comprises automatically checkingdesign rules that specify a minimum distance between the phase shifterand other structures within the integrated circuit.
 13. Thecomputer-readable storage medium of claim 9, wherein the method furthercomprises marking the endcap to prevent subsequent optical proximitycorrection (OPC) of the endcap.
 14. The computer-readable storage mediumof claim 13, wherein the method further comprises applying opticalproximity correction (OPC) to the specification of the integratedcircuit, wherein the OPC is not applied to endcaps that have beenmarked.
 15. The computer-readable storage medium of claim 9, wherein themethod further comprises removing the modifications to the endcap thatwere previously made for optical proximity correction (OPC).
 16. Thecomputer-readable storage medium of claim 9, wherein the method furthercomprises replacing the endcap with a straight endcap if the endcap isnot straight.
 17. A mask for use in fabricating an integrated circuit,wherein the mask includes a phase shifter that defines a gate, whereinthe phase shifter extends into an endcap of an associated transistor tocontrol line end shortening arising from optical effects, comprising:the phase shifter within the mask that is configured to create a regionof destructive light interference on a photoresist layer; wherein thephase shifter defines the gate within the associated transistor thatincludes the endcap that is susceptible to line end shortening during anoptical lithography process; wherein the phase shifter extends beyond anassociated active region of the associated transistor, so that the phaseshifter defines at least a portion of the endcap and thereby reducesline end shortening of the endcap due to optical effects.
 18. The maskof claim 17, wherein the phase shifter extends past the endcap.
 19. Themask of claim 17, wherein the phase shifter covers at least part of theendcap, but does not extend past the endcap.
 20. The mask of claim 17,wherein the phase shifter satisfies design rules that specify a minimumdistance between the phase shifter and other structures within theintegrated circuit.
 21. The mask of claim 17, further comprising asecond mask that defines binary features of the integrated circuit,wherein the second mask does not include any binary features for opticalproximity correction (OPC) of the endcap.
 22. The mask of claim 17,further comprising a second mask that defines binary features of theintegrated circuit, wherein the second mask includes binary features foroptical proximity correction (OPC) of other endcaps.
 23. A semiconductorstructure within an integrated circuit that is formed through a processthat controls line end shortening arising from optical effects, thesemiconductor structure comprising: a first transistor including a firstgate; wherein the first gate includes an endcap that is susceptible toline end shortening during an optical lithography process; wherein theendcap is formed by extending a phase shifter used to form the firstgate beyond an associated active region, so that the phase shifterdefines at least a portion of the endcap and thereby reduces line endshortening of the endcap due to optical effects.
 24. The semiconductorstructure of claim 23, wherein the phase shifter extends past theendcap.
 25. The semiconductor structure of claim 23, wherein the phaseshifter covers at least part of the endcap, but does not extend past theendcap.
 26. A system for reducing line end shortening during an opticallithography process for manufacturing an integrated circuit, comprising:a first means for receiving a specification of the integrated circuit,wherein the specification defines transistors that include gates; asecond means for identifying a gate within the specification, whereinthe gate includes an endcap that is susceptible to line end shorteningduring the optical lithography process; and a third means for extendinga phase shifter used to form the gate beyond an associated activeregion, so that the phase shifter defines at least a portion of theendcap and thereby reduces line end shortening of the endcap due tooptical effects.
 27. A method for reducing line end shortening during anoptical lithography process for manufacturing an integrated circuit,comprising: receiving a specification of the integrated circuit, whereinthe specification defines transistors that include gates; identifying agate within the specification, wherein the gate includes an endcap thatis susceptible to line end shortening during the optical lithographyprocess; and using an extended a phase shifter to form the gate, whereinthe extended phase shifter defines at least a portion of the endcap andthereby reduces line end shortening of the endcap due to opticaleffects.
 28. A mask for use in fabricating an integrated circuit,wherein the mask includes a phase shifter that defines a gate, whereinthe phase shifter extends into an endcap of an associated transistor tocontrol line end shortening arising from optical effects, comprising:the phase shifter within the mask that is configured to create a regionof destructive light interference on a photoresist layer; wherein thephase shifter defines the gate within the associated transistor thatincludes the endcap; wherein the phase shifter defines at least aportion of the endcap and thereby reduces line end shortening of theendcap due to optical effects.